Finding
Paper
Citations: 2
Abstract
Gate CD control is crucial to transistor fabrication for advanced technology nodes at and beyond 65 nm. ACLV (across chip linewidth variation) has been identified as a major contributor to overall CD budget for low k1 lithography. In this paper, we present a detailed characterization of ACLV performance on the latest ASML scanner using Texas Instruments proprietary scatterometer based lens fingerprinting technique (ScatterLith). We are able to decompose a complex ACLV signature including patterns placed in both vertical and horizontal directions and trace the CD errors back to various scanner components such as lens aberrations, illumination source shape, dynamic image field, and scan synchronization. Lithography simulation plays an important role in bringing together the wafer and tool metrology for direct correlation and providing a quantitative understanding of pattern sensitivity to lens and illuminator errors for a particular process setup. A new ACLV characterization methodology is enabled by combining wafer metrology ScattereLith, scanner metrology and lithography simulation. Implementation of this methodology improves tool-to-tool matching and control on ACLV and V-H bias across multiple scanners to meet tight yield and speed requirements for advanced chip manufacturing.
Authors
Changan Wang, Guohong Zhang, S. DeMoor
Journal
Journal name not available for this finding