Our intermediate results show that both the FPGA and ASIC accel-erators provide real-time inference performance for the analyzed network models at a reasonable implementation cost.

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)

The goal of the H2020 SELENE project is the development of a flexible computing platform for autonomous applications that includes built-in hardware support for safety. The SELENE computing platform is an open-source RISC-V heterogeneous multicore system-on-chip (SoC) that includes 6 NOEL-V RISC-V cores and artificial intelligence accelerators. In this paper, we describe the approach followed in the SELENE project to accelerate neural network inference processes. Our intermediate results show that both the FPGA and ASIC accel-erators provide real-time inference performance for the analyzed network models at a reasonable implementation cost.

Our intermediate results show that both the FPGA and ASIC accel-erators provide real-time inference performance for the analyzed network models at a reasonable implementation cost.

The SELENE Deep Learning Acceleration Framework for Safety-related Applications