The architecture of a character-serial systolic ring floating point multiply-accumulator is described. The performance of a rectangular systolic array of these processors is analyzed. The analysis may be used to optimize the specifications of the arithmetic elements under the particular constraints of area and bandwidth. An optimum architecture is defined for a particular class of gallium arsenide logic.<<ETX>>

This paper presents an optimal architecture for systolic ring processors for matrix computations, optimizing performance under area and bandwidth constraints for a specific class of gallium arsenide logic.

The architecture and optimisation of systolic ring processors for matrix computations

Key Takeaway: This paper presents an optimal architecture for systolic ring processors for matrix computations, optimizing performance under area and bandwidth constraints for a specific class of gallium arsenide logic.