S. Killge, V. Neumann, J. Bartha
Journal name not available for this finding
Electrical copper-based through-silicon vias (TSVs) are key elements for vertical connections in 3D interposer chip stacks. For the fabrication of such a chip stack, TSV structures with high aspect ratios (AR) of more than ten are necessary. The following contribution presents several of the key technical challenges associated with TSV fabrications. They include: silicon etching, insulator, barrier- and seed-layer material system deposition by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and electrochemical deposition (ECD) of TSV copper fills. Additionally we describe a process for interconnecting and bumping using solder bumps to realize an Si-based interposer as 3D chip stack. To meet these challenges, a process for fabricating high aspect ratio TSVs is presented. The process has been implemented and is shown to result in TSVs with aspect ratios from 10:1 up to 20:1 in thinned 200 μm thick wafer with 10–40 μm in TSV diameter.