Estimating Error Rate during Self-Test via One's Counting
Shideh Shahidi, S. Gupta
Oct 1, 2006
Citations
29
Citations
Journal
2006 IEEE International Test Conference
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Key Takeaway Key Takeaway: This paper proposes a low-cost self-test technique that estimates error rates in circuits under test, enabling identification of acceptable chips for various applications.
Abstract
We have shown previously that in many applications - including audio, speech, graphics, video, and digital communications - chips that cause occasional errors may lead to acceptable system operation, provided the rate at which errors occur at the output is below a desired threshold. In this paper we propose a new self-test technique to estimate the error rate, i.e., the percentage of input vectors likely to cause errors, for a circuit under test (CUT). The proposed method uses one's count signature to estimate the error rate at the output of the CUT. It then compares this estimate with a threshold error rate to decide whether the chip is acceptable for a particular application. Using this method, a large fraction of imperfect chips that can provide acceptable system operation can be identified, effectively leading to yield gain compared to classical test approaches. The fact that this yield gain is achievable using a low-cost self-test approach accentuates the economic benefits