Sung-Kun Park, Donghyun Woo, Min-Ki Na
Sep 1, 2017
2017 47th European Solid-State Device Research Conference (ESSDERC)
This paper reports the epitaxial-Si growth and dopant diffusion characteristics during fabrication of a vertical thin poly-Si channel (VTPC) transfer gate (TG) structured pixel, which is a possible candidate for future three-dimensional (3D) CMOS image sensor (CIS). Due to the increasing demand for higher resolution sensor, major CIS companies have presented various innovative 3D pixel structures of their own design. Recently, by adopting a structural concept similar to that of 3D NAND flash memories, a VTPC-TG structured pixel has been reported. However, grain boundary control and dopant diffusion behaviors in poly-Si have not been identified. The proposed process integration can suppress the dark current caused by grains of poly-Si in the VTPC-TG structured pixel by low temperature solid phase epitaxial growth. In addition, the channel punch-through caused by fast dopant diffusion in poly-Si can be suppressed by a thin poly-Si channel structure and process optimization.