M. Ikeda, T. Okubo, Tetsuya Abe
Mar 11, 1996
Proceedings ED&TC European Design and Test Conference
This paper presents a design for a real-time MPEG2 SP@ML video-encoder chip set. Its main features are: hardware/software partitioning based on a software encoder analysis, and a pipeline architecture where hardware and software interact closely and smoothly. We use a hardware/software concurrent design technique with fast verification to avoid major modifications at architectural and RTL levels. The chips were successfully fabricated with 0.5-/spl mu/m CMOS technology.