A Novel Circuit Design Methodology to Reduce Side Channel Leakage

doi:10.1007/978-3-642-34416-9_1

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A Novel Circuit Design Methodology to Reduce Side Channel Leakage

Andreas Gornik, I. Stoychev, J. Oehm

Nov 3, 2012

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Key Takeaway

Key Takeaway: This novel circuit design methodology effectively reduces side channel leakage in logic circuits, improving the overall performance of the circuit.

Abstract

To estimate the probable information leakage of a logic circuit through a side channel is a major problem for circuit designers. In this paper a novel circuit design methodology is presented to estimate and reduce the side channel leakage of logic gates. The focus lies on the investigation of side channel leakage during circuit design. With this novel methodology three different logic circuit families are compared. Additionally, the process of improving a logic circuit using this methodology is shown in detail.

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