V. Zhabin, V. Zhabina, O. Verba
Oct 5, 2020
2020 IEEE 2nd International Conference on System Analysis & Intelligent Computing (SAIC)
Computing systems, where computation units are directly connected in accordance with a data flow graph, are considered. In the computation units operations are executed in redundant symmetrical number system. It allows to overlap digit-by-digit input of operands, their processing and digit-by-digit output that starts from their high digits. A generated result digit does not need further correction and can be used as an operand digit on the next step of computation in other units. It enables to perform sequences of operations connected by means of data in concurrency mode at the level of operand digit processing. There is proposed an algorithm and architecture of a computation unit that enables to perform operations with the floating-point numbers in on-line mode with asynchronous data transmission between units. It enables to expand the range of processed data as well as to accelerate their processing. It is shown that digit-by-digit data processing gives an opportunity to reduce the required number of internal connections between the computation units, as well as of the chip pins. Due to the above mentioned, there is a potential possibility to place systems that require more hardware resources at one chip. It increases the reliability of systems and accelerates data processing.