Amr Lotfy, M. Ghoneima, M. Abdel-Moneum
Nov 1, 2011
2011 International Conference on Energy Aware Computing
In this paper a novel power gated digitally controlled oscillator (DCO) is presented. The DCO is suitable for integration in various systems such as clock generation circuits, clock and data recovery, and clocking schemes for high speed links. Simulations of the proposed DCO on 65nm TSMC technology show frequency range of 2.5 GHz to 6.8 GHz across all corners. The proposed DCO consumes only 1.7 mW at 3 GHz and 3.2 mW at 6.8 GHz with estimated layout area of 70∗70 μm2. The phase noise of the free running DCO is −92 dBc/Hz measured at 1 MHz offset from a 3.4 GHz center frequency.