Paper
15.2 A 1024-Channel 0.00029mm2/ch 74nW/ch Online Spatial Spike-Sorting Chip with Event-Driven Spike Detection and Self-Organizing Map Clustering
Published Feb 16, 2025 · Arash Akhoundi, Yawende Landbrug, Pumiao Yan
2025 IEEE International Solid-State Circuits Conference (ISSCC)
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Abstract
Next-generation brain-computer interfaces will enable motor and speech decoding in humans [1]–[3] and improve our understanding of brain function [4]. To achieve this requires high-density multi-electrode arrays (HD-MEA) [5], [6]. This leads to massive amounts of raw data that must be reduced on-chip to enable wireless operation [7]. Spike sorting (SS) assigns spikes to putative neurons and can reduce the data rate substantially because only the neuron ID needs to be transmitted when a spike occurs. Prior art focuses on improving the scalability and power efficiency of on-chip SS [8]–[15]. However, they either require a large input buffer [12]–[14], use temporal features (TF) that do not scale well to multi-channel systems [8]–[13], access the entire clustering memory for every spike [11]–[13], or use high power [8]–[11] and area [8]–[10]. This work uses event-driven spike detection and spatial spike sorting to deal with these challenges and achieve 74nW/ch, 0.00029mm2/ch, and <50μs latency with 1024 channels. This represents a >10x improvement in power and area efficiency with 3x more channels than prior art (Fig. 15.2.6).
This work demonstrates a 1024-channel spatial spike-sorting chip with event-driven spike detection and self-organizing map clustering, achieving 74nW/ch, 0.00029mm2/ch, and 50s latency, significantly improving power and area efficiency compared to prior art.
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