Does grain boundaries cause charge carrier traps in organic semiconductors?
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Grain Boundaries and Charge Carrier Traps in Organic Semiconductors
Introduction to Grain Boundaries in Organic Semiconductors
Grain boundaries (GBs) in organic semiconductors are critical structural features that significantly influence the electronic properties of devices such as light-emitting diodes, solar cells, and transistors. These boundaries, which occur at the interfaces between crystalline regions, can act as barriers or traps for charge carriers, thereby affecting the overall performance of the semiconductor devices.
Charge Carrier Traps at Grain Boundaries
Evidence of Charge Trapping
Several studies have demonstrated that grain boundaries can indeed act as traps for charge carriers. For instance, research on naphthalene polycrystals has shown the existence of trap states produced by grain boundaries, which hinder charge transport. Similarly, in polycrystalline pentacene and oligothiophene thin film devices, grain boundaries with acceptor-like trap levels form potential wells that trap charges, affecting the field-effect mobility.
Mechanisms of Trap Formation
The formation of trap states at grain boundaries can be attributed to various mechanisms. In CsPbBr3 perovskite solar cells, grain boundary sliding and distortion on a nanosecond timescale induce trap states through Pb-Pb interactions, leading to midgap states that trap charge carriers. Additionally, in organic field-effect transistors (OFETs), grain boundaries can act as traps or barriers, influencing the position of the Fermi level and the mode of charge transport.
Energy Barriers at Grain Boundaries
Dominance of Energy Barriers
While charge trapping is a significant issue, energy barriers at grain boundaries also play a crucial role in charge carrier transport. In perylene diimide thin films, energetic barriers at grain boundaries dominate charge transport, overshadowing the effects of previously identified grain-boundary defects. This indicates that the energy landscape at grain boundaries is a critical factor in determining the efficiency of charge transport.
Quantifying Energy Barriers
The activation energy for charge transport across grain boundaries has been quantified in various studies. For example, in triethylsilylethynyl anthradithiophene (TES ADT) spherulites, the activation energy increases from 34 meV within a spherulite to 50-66 meV across a boundary, depending on the molecular mismatch angle. This increase in activation energy highlights the impact of grain boundaries on charge transport efficiency.
Mitigating the Effects of Grain Boundaries
Molecular Design and Processing Techniques
To mitigate the detrimental effects of grain boundaries, several strategies have been proposed. Molecular design criteria can be derived to suppress energetic barriers at grain boundaries, leading to more efficient organic semiconductors. Additionally, processing techniques such as annealing and passivation can help alleviate the effects of grain boundary distortions and trap states in perovskites.
Optimizing Grain Boundary Microstructure
The microstructure of grain boundaries can be engineered to optimize charge transport. For instance, in PDI8-CN2 films, the molecular packing motif at grain boundaries significantly modulates carrier mobility, with different orientations leading to variations in transport efficiency by approximately two orders of magnitude. Understanding and controlling the microstructure at grain boundaries is thus essential for improving device performance.
Conclusion
Grain boundaries in organic semiconductors are critical determinants of charge carrier transport, acting as both traps and energy barriers. While charge trapping at grain boundaries can hinder device performance, the presence of energy barriers can also dominate charge transport. Mitigating these effects through molecular design, processing techniques, and microstructural optimization is essential for developing more efficient organic semiconductor devices.
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